module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q);

    wire		num;
    
    always @(posedge clk) begin
        if(reset) begin
           	q <= 4'd0; 
        end
        else begin
            if(slowena) begin
                if(q == 4'd9) begin
                    q <= 4'd0;
                end
                else begin
                   	q <= q + 1'b1; 
                end
            end
            else begin
               	q <= q; 
            end
        end
    end
/*    
    always @(posedge clk) begin
        if(reset) begin
           	num <= 1'b0; 
        end
        else begin
            if(slowena) begin
               	num <= 1'b1; 
            end
            else begin
                num <= 1'b0;
            end
        end
    end
*/
    
endmodule
